stm32 /stm32h5 /STM32H573 /GPDMA1 /GPDMA_RCFGLOCKR

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Interpret as GPDMA_RCFGLOCKR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LOCK0 0 (B_0x0)LOCK1 0 (B_0x0)LOCK2 0 (B_0x0)LOCK3 0 (B_0x0)LOCK4 0 (B_0x0)LOCK5 0 (B_0x0)LOCK6 0 (B_0x0)LOCK7

LOCK3=B_0x0, LOCK4=B_0x0, LOCK0=B_0x0, LOCK6=B_0x0, LOCK2=B_0x0, LOCK7=B_0x0, LOCK5=B_0x0, LOCK1=B_0x0

Description

GPDMA configuration lock register

Fields

LOCK0

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK1

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK2

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK3

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK4

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK5

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK6

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

LOCK7

lock the configuration of GPDMA_SECCFGR.SECx and GPDMA_PRIVCFGR.PRIVx, until a global GPDMA reset (x = 7 to 0) This bit is cleared after reset and, once set, it cannot be reset until a global GPDMA reset.

0 (B_0x0): secure privilege configuration of the channel x is writable.

1 (B_0x1): secure privilege configuration of the channel x is not writable.

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