DINNE=B_0x0, DCIS=B_0x0, DINIS=B_0x0, BUSY=B_0x0, DMAS=B_0x0
HASH status register
| DINIS | Data input interrupt status This bit is set by hardware when the FIFO is ready to get a new block (16 locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN register. When DINIS = 0, HASH_CSRx registers reads as zero. 0 (B_0x0): Less than 16 locations are free in the input buffer 1 (B_0x1): A new block can be entered into the input buffer. An interrupt is generated if the DINIE bit is set in the HASH_IMR register. |
| DCIS | Digest calculation completion interrupt status This bit is set by hardware when a digest becomes ready (the whole message has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1 in the HASH_CR register. 0 (B_0x0): No digest available in the HASH_HRx registers (zeros are returned) 1 (B_0x1): Digest calculation complete, a digest is available in the HASH_HRx registers. An interrupt is generated if the DCIE bit is set in the HASH_IMR register. |
| DMAS | DMA Status This bit provides information on the DMA interface activity. It is set with DMAE and cleared when DMAE = 0 and no DMA transfer is ongoing. No interrupt is associated with this bit. 0 (B_0x0): DMA interface is disabled (DMAE = 0) and no transfer is ongoing 1 (B_0x1): DMA interface is enabled (DMAE = 1) or a transfer is ongoing |
| BUSY | Busy bit 0 (B_0x0): No block is currently being processed 1 (B_0x1): The hash core is processing a block of data |
| NBWP | Number of words already pushed This bitfield is the exact number of words in the message that have already been pushed into the FIFO. NBWP is incremented by 1 when a write access is performed to the HASH_DIN register. When a digest calculation starts, NBWP is updated to NBWP- block size (in words), and NBWP goes to zero when the INIT bit is written to 1. |
| DINNE | DIN not empty This bit is set when the HASH_DIN register holds valid data (that is after being written at least once). It is cleared when either the INIT bit (initialization) or the DCAL bit (completion of the previous message processing) is written to 1. 0 (B_0x0): No data are present in the data input buffer 1 (B_0x1): The input buffer contains at least one word of data |
| NBWE | Number of words expected This bitfield reflects the number of words in the message that must be pushed into the FIFO to trigger a partial computation. NBWE is decremented by 1 when a write access is performed to the HASH_DIN register. NBWE is set to the expected block size +1 in words (0x11) when INIT bit is set in HASH_CR. It is set to the expected block size (0x10) when the partial digest calculation ends. |