MEND=B_0x0, DCNT=B_0x0
I3C message control register alternate
| DCNT | count of data to transfer during a read or write message, in bytes (when I3C is acting as controller) Linear encoding up to 64 Kbytes -1. … 0 (B_0x0): no data to transfer (allowed for write message and only for GET CCC read commands. Mandated value when emitting ENTDAA) 1 (B_0x1): 1 byte 2 (B_0x2): 2 bytes 65535 (B_0xFFFF): 64 Kbytes 1 byte |
| CCC | 8-bit CCC code (when I3C is acting as controller) If Bit[23]=CCC[7]=1, this is the 1st part of an I3C SDR direct CCC command. If Bit[23]=CCC[7]=0, this is an I3C SDR broadcast CCC command (including ENTDAA and ENTHDR0). |
| MTYPE | message type (when I3C is acting as controller) Bits[23:16] (CCC[7:0]) is the emitted 8-bit CCC code If Bit[23]=CCC[7]=1: this is the 1st part of an I3C SDR direct CCC command The transferred direct CCC command message is: {S / S+7’h7E +RnW=0 / Sr+} + (direct CCC + T) + (8-bit Data + T) + Sr After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+R/W). If Bit[23]=CCC[7]=0: this is an I3C SDR broadcast CCC command (including ENTDAA and ENTHDR0) The transferred broadcast CCC command message is: {S / S+7’h7E +RnW=0 / Sr+} + (broadcast CCC + T) + (8-bit Data + T)* + Sr/P After a S (START), depending on I3C_CFGR.NOARBH, the arbitrable header (7’h7E+RnW=0) is inserted or not. Sr+*: after a Sr (Repeated Start), the hardware automatically inserts (7’h7E+R/W). others: reserved 6 (B_0x6_WHEN_I3C_IS_ACTING_AS_I3C_CONTROLLER): CCC command |
| MEND | message end type (when I3C is acting as controller) 0 (B_0x0): this message from the controller ends with a Repeated START (Sr) 1 (B_0x1): the message from the controller ends with a STOP (P), being the last message of a frame |