stm32 /stm32h5 /STM32H573 /ICACHE /ICACHE_CRR0

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Interpret as ICACHE_CRR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BASEADDR0RSIZE0 (B_0x0)REN 0REMAPADDR0 (B_0x0)MSTSEL 0 (B_0x0)HBURST

REN=B_0x0, MSTSEL=B_0x0, HBURST=B_0x0

Description

ICACHE region 0 configuration register

Fields

BASEADDR

base address for region x This alias address is replaced by REMAPADDR field. The only useful bits are [28:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see ). If the programmed value has more LSBs, the useless bits are ignored.

RSIZE

size for region x

1 (B_0x1): 2 Mbytes

2 (B_0x2): 4 Mbytes

3 (B_0x3): 8 Mbytes

4 (B_0x4): 16 Mbytes

5 (B_0x5): 32 Mbytes

6 (B_0x6): 64 Mbytes

7 (B_0x7): 128 Mbytes

REN

enable for region x

0 (B_0x0): disabled

1 (B_0x1): enabled

REMAPADDR

remapped address for region x This field replaces the alias address defined by BASEADDR field. The only useful bits are [31:RI], where 21 less than or equal RI less than or equal 27 is the number of bits of RSIZE (see ). If the programmed value has more LSBs, the useless bits are ignored.

MSTSEL

AHB cache master selection for region x

0 (B_0x0): no action (master1 selected by default)

1 (B_0x1): master2 selected

HBURST

output burst type for region x

0 (B_0x0): WRAP

1 (B_0x1): INCR

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