stm32 /stm32h5 /STM32H573 /RCC /RCC_AHB1LPENR

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Interpret as RCC_AHB1LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)GPDMA1LPEN 0 (B_0x0)GPDMA2LPEN 0 (B_0x0)FLITFLPEN 0 (B_0x0)CRCLPEN 0 (B_0x0)CORDICLPEN 0 (B_0x0)FMACLPEN 0 (B_0x0)RAMCFGLPEN 0 (B_0x0)ETHLPEN 0 (B_0x0)ETHTXLPEN 0 (B_0x0)ETHRXLPEN 0 (B_0x0)TZSC1LPEN 0 (B_0x0)BKPRAMLPEN 0 (B_0x0)ICACHELPEN 0 (B_0x0)DCACHELPEN 0 (B_0x0)SRAM1LPEN

ETHTXLPEN=B_0x0, ICACHELPEN=B_0x0, BKPRAMLPEN=B_0x0, GPDMA1LPEN=B_0x0, ETHLPEN=B_0x0, RAMCFGLPEN=B_0x0, SRAM1LPEN=B_0x0, CORDICLPEN=B_0x0, DCACHELPEN=B_0x0, ETHRXLPEN=B_0x0, GPDMA2LPEN=B_0x0, CRCLPEN=B_0x0, FLITFLPEN=B_0x0, TZSC1LPEN=B_0x0, FMACLPEN=B_0x0

Description

RCC AHB1 sleep clock register

Fields

GPDMA1LPEN

GPDMA1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPDMA1 peripheral clock disabled during sleep mode

1 (B_0x1): GPDMA1 peripheral clock enabled during sleep mode (default after reset)

GPDMA2LPEN

GPDMA2 clock enable during sleep mode Set and reset by software.

0 (B_0x0): GPDMA2 peripheral clock disabled during sleep mode

1 (B_0x1): GPDMA2 peripheral clock enabled during sleep mode (default after reset)

FLITFLPEN

Flash interface (FLITF) clock enable during sleep mode Set and reset by software.

0 (B_0x0): FLITF peripheral clock disabled during sleep mode

1 (B_0x1): FLITF peripheral clock enabled during sleep mode (default after reset)

CRCLPEN

CRC clock enable during sleep mode Set and reset by software.

0 (B_0x0): CRC peripheral clock disabled during sleep mode

1 (B_0x1): CRC peripheral clock enabled during sleep mode (default after reset)

CORDICLPEN

CORDIC clock enable during sleep mode Set and reset by software.

0 (B_0x0): CORDIC peripheral clock disabled during sleep mode

1 (B_0x1): CORDIC peripheral clock enabled during sleep mode (default after reset)

FMACLPEN

FMAC clock enable during sleep mode Set and reset by software.

0 (B_0x0): FMAC peripheral clock disabled during sleep mode

1 (B_0x1): FMAC peripheral clock enabled during sleep mode (default after reset)

RAMCFGLPEN

RAMCFG clock enable during sleep mode Set and reset by software.

0 (B_0x0): RAMCFG peripheral clock disabled during sleep mode

1 (B_0x1): RAMCFG peripheral clock enabled during sleep mode (default after reset)

ETHLPEN

ETH clock enable during Sleep mode Set and reset by software

0 (B_0x0): ETH peripheral clock disabled during sleep mode

1 (B_0x1): ETH peripheral clock enabled during Sleep mode (default after reset)

ETHTXLPEN

ETHTX clock enable during sleep mode Set and reset by software

0 (B_0x0): ETHTX clock disabled during sleep mode

1 (B_0x1): ETHTX clock enabled during sleep mode (default after reset)

ETHRXLPEN

ETHRX clock enable during sleep mode Set and reset by software

0 (B_0x0): ETHRX clock disabled during sleep mode

1 (B_0x1): ETHRX clock enabled during sleep mode (default after reset)

TZSC1LPEN

TZSC1 clock enable during sleep mode Set and reset by software

0 (B_0x0): TZSC1 peripheral clock disabled during sleep mode

1 (B_0x1): TZSC1 peripheral clock enabled during sleep mode (default after reset)

BKPRAMLPEN

BKPRAM clock enable during sleep mode Set and reset by software

0 (B_0x0): BKPRAM peripheral clock disabled during sleep mode

1 (B_0x1): BKPRAM peripheral clock enabled during sleep mode (default after reset)

ICACHELPEN

ICACHE clock enable during sleep mode Set and reset by software

0 (B_0x0): ICACHE peripheral clock disabled during sleep mode

1 (B_0x1): ICACHE peripheral clock enabled during sleep mode (default after reset)

DCACHELPEN

DCACHE clock enable during sleep mode Set and reset by software

0 (B_0x0): DCACHE peripheral clock disabled during sleep mode

1 (B_0x1): DCACHE peripheral clock enabled during sleep mode (default after reset)

SRAM1LPEN

SRAM1 clock enable during sleep mode Set and reset by software

0 (B_0x0): SRAM1 peripheral clock disabled during sleep mode

1 (B_0x1): SRAM1 peripheral clock enabled during sleep mode (default after reset)

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