UCPDEN=B_0x0, UART12EN=B_0x0, DTSEN=B_0x0, UART9EN=B_0x0, LPTIM2EN=B_0x0, FDCAN12EN=B_0x0
RCC APB1 peripheral clock register
| UART9EN | UART9 clock enable Set and reset by software. 0 (B_0x0): UART9 peripheral clock disabled (default after reset) 1 (B_0x1): resets UART9 peripheral clock enabled |
| UART12EN | UART12 clock enable Set and reset by software. 0 (B_0x0): UART12 peripheral clock disabled (default after reset) 1 (B_0x1): UART12 peripheral clock enabled |
| DTSEN | DTS clock enable Set and reset by software. 0 (B_0x0): DTS peripheral clock disabled (default after reset) 1 (B_0x1): DTS peripheral clock enabled |
| LPTIM2EN | LPTIM2 clock enable Set and reset by software. 0 (B_0x0): LPTIM2 peripheral clock disabled (default after reset) 1 (B_0x1): LPTIM2 peripheral clock enabled |
| FDCAN12EN | FDCAN1 and FDCAN2 peripheral clock enable Set and reset by software. 0 (B_0x0): FDCAN1 and FDCAN2 peripheral clock disabled (default after reset) 1 (B_0x1): FDCAN1 and FDCAN2 peripheral clock enabled |
| UCPDEN | UCPD clock enable Set and reset by software. 0 (B_0x0): UCPD peripheral clock disabled (default after reset) 1 (B_0x1): UCPD peripheral clock enabled |