stm32 /stm32h5 /STM32H573 /RCC /RCC_APB3LPENR

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Interpret as RCC_APB3LPENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SBSLPEN 0 (B_0x0)SPI5LPEN 0 (B_0x0)LPUART1LPEN 0 (B_0x0)I2C3LPEN 0 (B_0x0)I2C4LPEN 0 (B_0x0)LPTIM1LPEN 0 (B_0x0)LPTIM3LPEN 0 (B_0x0)LPTIM4LPEN 0 (B_0x0)LPTIM5LPEN 0 (B_0x0)LPTIM6LPEN 0 (B_0x0)VREFLPEN 0 (B_0x0)RTCAPBLPEN

VREFLPEN=B_0x0, RTCAPBLPEN=B_0x0, LPTIM3LPEN=B_0x0, SPI5LPEN=B_0x0, I2C4LPEN=B_0x0, SBSLPEN=B_0x0, LPTIM1LPEN=B_0x0, LPTIM4LPEN=B_0x0, I2C3LPEN=B_0x0, LPUART1LPEN=B_0x0, LPTIM5LPEN=B_0x0, LPTIM6LPEN=B_0x0

Description

RCC APB4 sleep clock register

Fields

SBSLPEN

SBS clock enable during sleep mode Set and reset by software.

0 (B_0x0): SBS peripheral clock disabled during sleep mode

1 (B_0x1): SBS peripheral clock enabled during sleep mode (default after reset)

SPI5LPEN

SPI5 clock enable during Slsleepeep mode Set and reset by software.

0 (B_0x0): SPI5 peripheral clock disabled during sleep mode

1 (B_0x1): SPI5 peripheral clock enabled during Slesleepep mode (default after reset)

LPUART1LPEN

LPUART1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPUART1 peripheral clock disabled during sleep mode

1 (B_0x1): LPUART1 peripheral clock enabled during sleep mode (default after reset)

I2C3LPEN

I2C3 clock enable during sleep mode Set and reset by software.

0 (B_0x0): I2C3 peripheral clock disabled during sleep mode

1 (B_0x1): I2C3 peripheral clock enabled during sleep mode (default after reset)

I2C4LPEN

I2C4 clock enable during sleep mode Set and reset by software.

0 (B_0x0): I2C4 peripheral clock disabled during sleep mode

1 (B_0x1): I2C4 peripheral clock enabled during sleep mode (default after reset)

LPTIM1LPEN

LPTIM1 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM1 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM1 peripheral clock enabled during sleep mode (default after reset)

LPTIM3LPEN

LPTIM3 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM3 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM3 peripheral clock enabled during sleep mode (default after reset)

LPTIM4LPEN

LPTIM4 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM4 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM4 peripheral clock enabled during sleep mode (default after reset)

LPTIM5LPEN

LPTIM5 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM5 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM5 peripheral clock enabled during sleep mode (default after reset)

LPTIM6LPEN

LPTIM6 clock enable during sleep mode Set and reset by software.

0 (B_0x0): LPTIM6 peripheral clock disabled during sleep mode

1 (B_0x1): LPTIM6 peripheral clock enabled during sleep mode (default after reset)

VREFLPEN

VREF clock enable during sleep mode Set and reset by software.

0 (B_0x0): VREF peripheral clock disabled during sleep mode

1 (B_0x1): VREF peripheral clock enabled during sleep mode (default after reset)

RTCAPBLPEN

RTC APB interface clock enable during sleep mode Set and reset by software.

0 (B_0x0): RTC APB interface clock disabled during sleep mode

1 (B_0x1): RTC APB interface clock enabled during sleep mode (default after reset)

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