RegViz: Visualize RCC_CCIPR1 Bitfield

stm32 /stm32h5 /STM32H573 /RCC /RCC_CCIPR1

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Interpret as RCC_CCIPR1

UART7SEL=B_0x0, UART9SEL=B_0x0, USART2SEL=B_0x0, USART6SEL=B_0x0, UART8SEL=B_0x0, USART3SEL=B_0x0, USART1SEL=B_0x0, UART4SEL=B_0x0, TIMICSEL=B_0x0, UART5SEL=B_0x0, USART10SEL=B_0x0

Description

RCC kernel clock configuration register

Fields

USART1SEL	USART1 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk2 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
USART2SEL	USART2 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
USART3SEL	USART3 kernel clock source selection Set and reset by software. others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
UART4SEL	UART4 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
UART5SEL	UART5 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
USART6SEL	USART6 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
UART7SEL	UART7 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
UART8SEL	UART8 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
UART9SEL	UART9 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
USART10SEL	USART10 kernel clock source selection others: reserved, the kernel clock is disabled 0 (B_0x0): rcc_pclk1 selected as kernel clock (default after reset) 1 (B_0x1): pll2_q_ck selected as kernel clock 2 (B_0x2): pll3_q_ck selected as kernel clock 3 (B_0x3): hsi_ker_ck selected as kernel clock 4 (B_0x4): csi_ker_ck selected as kernel clock 5 (B_0x5): lse_ck selected as kernel clock
TIMICSEL	TIM12, TIM15 and LPTIM2 input capture source selection Set and reset by software. 0 (B_0x0): No internal clock available for timers input capture (default after reset) 1 (B_0x1): hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture

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