stm32 /stm32h5 /STM32H573 /RCC /RCC_CFGR1

system clock and trace clock switch Set and reset by software to select system clock and trace clock sources (sys_ck). Set by hardware in order to:

• force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode
• force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock others: reserved

0 (B_0x0): HSI selected as system clock (hsi_ck) (default after reset)

1 (B_0x1): CSI selected as system clock (csi_ck)

2 (B_0x2): HSE selected as system clock (hse_ck)

3 (B_0x3): PLL1 selected as system clock (pll1_p_ck for sys_ck)

system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset). others: reserved

1 (B_0x1): CSI used as system clock (csi_ck)

2 (B_0x2): HSE used as system clock (hse_ck)

3 (B_0x3): PLL1 used as system clock (pll1_p_ck)

system clock selection after a wakeup from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset) STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).

1 (B_0x1): CSI selected as wakeup clock from system Stop

kernel clock selection after a wakeup from system Stop Set and reset by software to select the kernel wakeup clock from system Stop.

0 (B_0x0): HSI selected as wakeup clock from system Stop (default after reset)

1 (B_0x1): CSI selected as wakeup clock from system Stop

HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. …

0 (B_0x0): no clock (default after reset)

1 (B_0x1): no clock

2 (B_0x2): HSE/2

3 (B_0x3): HSE/3

4 (B_0x4): HSE/4

62 (B_0x3E): HSE/62

63 (B_0x3F): HSE/63

timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains.

0 (B_0x0): The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)

1 (B_0x1): The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2

MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. …

0 (B_0x0): prescaler disabled (default after reset)

1 (B_0x1): division by 1 (bypass)

2 (B_0x2): division by 2

3 (B_0x3): division by 3

4 (B_0x4): division by 4

15 (B_0xF): division by 15

Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved

0 (B_0x0): HSI clock selected (hsi_ck) (default after reset)

1 (B_0x1): LSE oscillator clock selected (lse_ck)

2 (B_0x2): HSE clock selected (hse_ck)

3 (B_0x3): PLL1 clock selected (pll1_q_ck)

4 (B_0x4): HSI48 clock selected (hsi48_ck)

MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. …

0 (B_0x0): prescaler disabled (default after reset)

1 (B_0x1): division by 1 (bypass)

2 (B_0x2): division by 2

3 (B_0x3): division by 3

4 (B_0x4): division by 4

15 (B_0xF): division by 15

microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved

0 (B_0x0): system clock selected (sys_ck) (default after reset)

1 (B_0x1): PLL2 oscillator clock selected (pll2_p_ck)

2 (B_0x2): HSE clock selected (hse_ck)

3 (B_0x3): PLL1 clock selected (pll1_p_ck)

4 (B_0x4): CSI clock selected (csi_ck)

5 (B_0x5): LSI clock selected (lsi_ck)