DIVM1=B_0x0, PLL1VCOSEL=B_0x0, PLL1RGE=B_0x0, PLL1REN=B_0x0, PLL1QEN=B_0x0, PLL1PEN=B_0x0
RCC PLL clock source selection register
| PLL1SRC | DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, the value of PLL1SRC must be set to ‘00’. 00: no clock send to DIVMx divider and PLLs (default after reset). 1 (B_0x1): HSI selected as PLL clock (hsi_ck) 2 (B_0x2): CSI selected as PLL clock (csi_ck) 3 (B_0x3): HSE selected as PLL clock (hse_ck) |
| PLL1RGE | PLL1 input frequency range Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1. 0 (B_0x0): PLL1 input (ref1_ck) clock range frequency between 1 and 2 MHz (default after reset) 1 (B_0x1): PLL1 input (ref1_ck) clock range frequency between 2 and 4 MHz 2 (B_0x2): PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 3 (B_0x3): PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz |
| PLL1FRACEN | PLL1 fractional latch enable Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator. In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator. |
| PLL1VCOSEL | PLL1 VCO selection Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1. 0 (B_0x0): wide VCO range 192 to 836 MHz (default after reset) 1 (B_0x1): medium VCO range 150 to 420 MHz |
| DIVM1 | prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. … … 0 (B_0x0): prescaler disabled (default after reset) 1 (B_0x1): division by 1 (bypass) 2 (B_0x2): division by 2 3 (B_0x3): division by 3 32 (B_0x20): division by 32 63 (B_0x3F): division by 63 |
| PLL1PEN | PLL1 DIVP divider output enable Set and reset by software to enable the pll1_p_ck output of the PLL1. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled. 0 (B_0x0): pll1_p_ck output disabled (default after reset) 1 (B_0x1): pll1_p_ck output enabled |
| PLL1QEN | PLL1 DIVQ divider output enable Set and reset by software to enable the pll1_q_ck output of the PLL1. In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1_q_ck output disabled (default after reset) 1 (B_0x1): pll1_q_ck output enabled |
| PLL1REN | PLL1 DIVR divider output enable Set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). 0 (B_0x0): pll1_r_ck output disabled (default after reset) 1 (B_0x1): pll1_r_ck output enabled |