stm32 /stm32h5 /STM32H573 /RCC /RCC_PLL1FRACR

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Interpret as RCC_PLL1FRACR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL1FRACN

Description

RCC PLL1 fractional divider register

Fields

PLL1FRACN

fractional part of the multiplication factor for PLL1 VCO Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:

  • 128 to 560 MHz if PLL1VCOSEL = 0
  • 150 to 420 MHz if PLL1VCOSEL = 1 VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with
  • PLL1N between 8 and 420
  • PLL1FRACN can be between 0 and 213- 1
  • The input frequency Fref1_ck must be between 1 and 16 MHz. To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:
  • Set the bit PLL1FRACEN to 0
  • Write the new fractional value into PLL1FRACN
  • Set the bit PLL1FRACEN to 1

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