stm32 /stm32h5 /STM32H573 /RCC /RCC_PLL3DIVR

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Interpret as RCC_PLL3DIVR

PLL3Q=B_0x0, PLL3P=B_0x0, PLL3R=B_0x0

Description

RCC PLL3 dividers register

Fields

PLL3N	Multiplication factor for PLL3VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). … … Others: reserved 3 (B_0x3): PLL3N = 4 4 (B_0x4): PLL3N = 5 5 (B_0x5): PLL3N = 6 128 (B_0x80): PLL3N = 129 (default after reset) 511 (B_0x1FF): PLL3N = 512
PLL3P	PLL3 DIVP division factor Set and reset by software to control the frequency of the pll3_p_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): pll3_p_ck = vco3_ck 1 (B_0x1): pll3_p_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_p_ck = vco3_ck / 3 3 (B_0x3): pll3_p_ck = vco3_ck / 4 127 (B_0x7F): pll3_p_ck = vco3_ck / 128
PLL3Q	PLL3 DIVQ division factor Set and reset by software to control the frequency of the pll3_q_ck clock. These bits can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): pll3_q_ck = vco3_ck 1 (B_0x1): pll3_q_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_q_ck = vco3_ck / 3 3 (B_0x3): pll3_q_ck = vco3_ck / 4 127 (B_0x7F): pll3_q_ck = vco3_ck / 128
PLL3R	PLL3 DIVR division factor Set and reset by software to control the frequency of the pll3_r_ck clock. These bits can be written only when the PLL1 is disabled (PLL3ON = 0 and PLL3RDY = 0). … 0 (B_0x0): pll3_r_ck = vco3_ck 1 (B_0x1): pll3_r_ck = vco3_ck / 2 (default after reset) 2 (B_0x2): pll3_r_ck = vco3_ck / 3 3 (B_0x3): pll3_r_ck = vco3_ck / 4 127 (B_0x7F): pll3_r_ck = vco3_ck / 128

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