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stm32 /stm32h5 /STM32H573 /SDMMC1 /SDMMC_IDMABAR

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Interpret as SDMMC_IDMABAR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IDMABA

Description

SDMMC_IDMABAR

Fields

IDMABA

Word aligned Linked list memory base address Linked list memory base pointer. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32