Regviz

stm32 /stm32h5 /STM32H573 /SDMMC1 /SDMMC_IDMABASER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SDMMC_IDMABASER

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H562/SDMMC1/SDMMC_IDMABASER#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IDMABASE

Description

SDMMC IDMA buffer base address register

Fields

IDMABASE

Buffer memory base address bits [31:2], must be word aligned (bit [1:0] are always 0 and read only) This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1).

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32