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stm32 /stm32h5 /STM32H573 /TIM15 /TIM15_DMAR

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Interpret as TIM15_DMAR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMAB

Description

TIM15 DMA address for full transfer

Fields

DMAB

DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIM15_CR1 address) + (DBA + DMA index) x 4 where TIM15_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM15_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM15_DCR).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32