MMS=B_0x0
TIM7 control register 2
| MMS | Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or he peripheral receiving the tim_trgo must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. 0 (B_0x0): Reset the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo). 1 (B_0x1): Enable the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written. 2 (B_0x2): Update The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer. |