RegViz: Visualize ADC_SMPR2 Bitfield

stm32 /stm32h7 /STM32H723 /ADC1 /ADC_SMPR2

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Interpret as ADC_SMPR2

SMP14=B_0x0, SMP17=B_0x0, SMP11=B_0x0, SMP18=B_0x0, SMP13=B_0x0, SMP12=B_0x0, SMP10=B_0x0, SMP19=B_0x0, SMP15=B_0x0, SMP16=B_0x0

Description

ADC sample time register 2

Fields

SMP10	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP11	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP12	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP13	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP14	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP15	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP16	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP17	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP18	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles
SMP19	Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). 0 (B_0x0): 1.5 ADC clock cycles 1 (B_0x1): 2.5 ADC clock cycles 2 (B_0x2): 8.5 ADC clock cycles 3 (B_0x3): 16.5 ADC clock cycles 4 (B_0x4): 32.5 ADC clock cycles 5 (B_0x5): 64.5 ADC clock cycles 6 (B_0x6): 387.5 ADC clock cycles 7 (B_0x7): 810.5 ADC clock cycles

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