RRDY=B_0x0, DMAREN=B_0x0, ARGSIZE=B_0x0, NARGS=B_0x0, IEN=B_0x0, NRES=B_0x0, FUNC=B_0x0, RESSIZE=B_0x0, DMAWEN=B_0x0
CORDIC control/status register
| FUNC | Function 0 (B_0x0): Cosine 1 (B_0x1): Sine |
| PRECISION | Precision required (number of iterations) To determine the number of iterations needed for a given accuracy refer to . Note that for most functions, the recommended range for this field is 3 to 6. 1 (B_0x1): (Number of iterations)/4 2 (B_0x2): (Number of iterations)/4 3 (B_0x3): (Number of iterations)/4 4 (B_0x4): (Number of iterations)/4 5 (B_0x5): (Number of iterations)/4 6 (B_0x6): (Number of iterations)/4 7 (B_0x7): (Number of iterations)/4 8 (B_0x8): (Number of iterations)/4 9 (B_0x9): (Number of iterations)/4 10 (B_0xa): (Number of iterations)/4 11 (B_0xb): (Number of iterations)/4 12 (B_0xc): (Number of iterations)/4 13 (B_0xd): (Number of iterations)/4 14 (B_0xe): (Number of iterations)/4 15 (B_0xf): (Number of iterations)/4 |
| SCALE | Scaling factor The value of this field indicates the scaling factor applied to the arguments and/or results. A value n implies that the arguments have been multiplied by a factor 2-n, and/or the results need to be multiplied by 2n. Refer to for the applicability of the scaling factor for each function and the appropriate range. |
| IEN | Enable interrupt. This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No interrupt requests are generated. 1 (B_0x1): Enabled. An interrupt request is generated whenever the RRDY flag is set. |
| DMAREN | Enable DMA read channel This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No DMA read requests are generated. 1 (B_0x1): Enabled. Requests are generated on the DMA read channel whenever the RRDY flag is set. |
| DMAWEN | Enable DMA write channel This bit is set and cleared by software. A read returns the current state of the bit. 0 (B_0x0): Disabled. No DMA write requests are generated. 1 (B_0x1): Enabled. Requests are generated on the DMA write channel whenever no operation is pending |
| NRES | Number of results in the CORDIC_RDATA register Reads return the current state of the bit. 0 (B_0x0): Only one 32-bit value (or two 16-bit values if RESSIZE = 1) is transferred to the CORDIC_RDATA register on completion of the next calculation. One read from CORDIC_RDATA resets the RRDY flag. 1 (B_0x1): Two 32-bit values are transferred to the CORDIC_RDATA register on completion of the next calculation. Two reads from CORDIC_RDATA are necessary to reset the RRDY flag. |
| NARGS | Number of arguments expected by the CORDIC_WDATA register Reads return the current state of the bit. 0 (B_0x0): Only one 32-bit write (or two 16-bit values if ARGSIZE = 1) is needed for the next calculation. 1 (B_0x1): Two 32-bit values must be written to the CORDIC_WDATA register to trigger the next calculation. |
| RESSIZE | Width of output data RESSIZE selects the number of bits used to represent output data. If 32-bit data is selected, the CORDIC_RDATA register contains results in q1.31 format. If 16-bit data is selected, the least significant half-word of CORDIC_RDATA contains the primary result (RES1) in q1.15 format, and the most significant half-word contains the secondary result (RES2), also in q1.15 format. 0 (B_0x0): 32-bit 1 (B_0x1): 16-bit |
| ARGSIZE | Width of input data ARGSIZE selects the number of bits used to represent input data. If 32-bit data is selected, the CORDIC_WDATA register expects arguments in q1.31 format. If 16-bit data is selected, the CORDIC_WDATA register expects arguments in q1.15 format. The primary argument (ARG1) is written to the least significant half-word, and the secondary argument (ARG2) to the most significant half-word. 0 (B_0x0): 32-bit 1 (B_0x1): 16-bit |
| RRDY | Result ready flag This bit is set by hardware when a CORDIC operation completes. It is reset by hardware when the CORDIC_RDATA register is read (NRES+1) times. When this bit is set, if the IEN bit is also set, the CORDIC interrupt is asserted. If the DMAREN bit is set, a DMA read channel request is generated. While this bit is set, no new calculation is started. 0 (B_0x0): No new result in output register 1 (B_0x1): CORDIC_RDATA register contains new data. |