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stm32 /stm32h7 /STM32H723 /Flash /CCR

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Interpret as CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLR_EOP)CLR_EOP 0 (CLR_WRPERR)CLR_WRPERR 0 (CLR_PGSERR)CLR_PGSERR 0 (CLR_STRBERR)CLR_STRBERR 0 (CLR_INCERR)CLR_INCERR 0 (CLR_OPERR)CLR_OPERR 0 (CLR_RDPERR)CLR_RDPERR 0 (CLR_RDSERR)CLR_RDSERR 0 (CLR_SNECCERR)CLR_SNECCERR 0 (CLR_DBECCERR)CLR_DBECCERR 0 (CLR_CRCEND)CLR_CRCEND 0 (CLR_CRCRDERR)CLR_CRCRDERR

Description

FLASH clear control register for bank 1

Fields

CLR_EOP

EOP1 flag clear bit
CLR_WRPERR

WRPERR1 flag clear bit
CLR_PGSERR

PGSERR flag clear bi
CLR_STRBERR

STRBERR flag clear bit
CLR_INCERR

INCERR flag clear bit
CLR_OPERR

OPERR flag clear bit
CLR_RDPERR

RDPERR flag clear bit
CLR_RDSERR

RDSERR flag clear bit
CLR_SNECCERR

SNECCERR flag clear bit
CLR_DBECCERR

DBECCERR flag clear bit
CLR_CRCEND

CRCEND flag clear bit
CLR_CRCRDERR

CRCRDERR1 flag clear bit Setting this bit to 1 resets to 0 CRCRDERR1 flag in FLASH_SR1 register.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32