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stm32 /stm32h7 /STM32H730 /ADC12_Common /CDR

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Interpret as CDR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RDATA_MST0RDATA_SLV

Description

ADC common regular data register for dual and triple modes

Fields

RDATA_MST

Regular data of the master ADC
RDATA_SLV

Regular data of the slave ADC

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32