PRESC=B_0x0, CKMODE=B_0x0, VBATEN=B_0x0, TSEN=B_0x0, VREFEN=B_0x0
ADC common control register
| CKMODE | ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 (B_0x0): adc_ker_ck (x = 3) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC)) 1 (B_0x1): adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0XXX in RCC_CFGR register) and if the system clock has a 50% duty cycle. 2 (B_0x2): adc_hclk/2 (Synchronous clock mode) 3 (B_0x3): adc_hclk/4 (Synchronous clock mode) |
| PRESC | ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00. 0 (B_0x0): input ADC clock not divided 1 (B_0x1): input ADC clock divided by 2 2 (B_0x2): input ADC clock divided by 4 3 (B_0x3): input ADC clock divided by 6 4 (B_0x4): input ADC clock divided by 8 5 (B_0x5): input ADC clock divided by 10 6 (B_0x6): input ADC clock divided by 12 7 (B_0x7): input ADC clock divided by 16 8 (B_0x8): input ADC clock divided by 32 9 (B_0x9): input ADC clock divided by 64 10 (B_0xA): input ADC clock divided by 128 11 (B_0xB): input ADC clock divided by 256 |
| VREFEN | VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel. 0 (B_0x0): VREFINT channel disabled 1 (B_0x1): VREFINT channel enabled |
| TSEN | VSENSE enable This bit is set and cleared by software to control VSENSE. 0 (B_0x0): Temperature sensor channel disabled 1 (B_0x1): Temperature sensor channel enabled |
| VBATEN | VBAT enable This bit is set and cleared by software to control. 0 (B_0x0): VBAT channel disabled 1 (B_0x1): VBAT channel enabled |