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stm32 /stm32h7 /STM32H730 /DBGMCU /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBGSLPD1)DBGSLPD1 0 (DBGSTPD1)DBGSTPD1 0 (DBGSTBD1)DBGSTBD1 0 (DBGSLPD2)DBGSLPD2 0 (DBGSTPD2)DBGSTPD2 0 (DBGSTBD2)DBGSTBD2 0 (DBGSTPD3)DBGSTPD3 0 (DBGSTBD3)DBGSTBD3 0 (TRACECLKEN)TRACECLKEN 0 (D1DBGCKEN)D1DBGCKEN 0 (D3DBGCKEN)D3DBGCKEN 0 (TRGOEN)TRGOEN

Description

DBGMCU Configuration Register

Fields

DBGSLPD1

Allow D1 domain debug in Sleep mode
DBGSTPD1

Allow D1 domain debug in Stop mode
DBGSTBD1

Allow D1 domain debug in Standby mode
DBGSLPD2

Allow D2 domain debug in Sleep mode
DBGSTPD2

Allow D2 domain debug in Stop mode
DBGSTBD2

Allow D2 domain debug in Standby mode
DBGSTPD3

Allow debug in D3 Stop mode
DBGSTBD3

Allow debug in D3 Standby mode
TRACECLKEN

Trace port clock enable
D1DBGCKEN

D1 debug clock enable
D3DBGCKEN

D3 debug clock enable
TRGOEN

External trigger output enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32