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stm32 /stm32h7 /STM32H730 /Ethernet_MAC /MACCR

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Interpret as MACCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RE)RE 0 (TE)TE 0PRELEN 0 (DC)DC 0BL0 (DR)DR 0 (DCRS)DCRS 0 (DO)DO 0 (ECRSFD)ECRSFD 0 (LM)LM 0 (DM)DM 0 (FES)FES 0 (JE)JE 0 (JD)JD 0 (WD)WD 0 (ACS)ACS 0 (CST)CST 0 (S2KP)S2KP 0 (GPSLCE)GPSLCE 0IPG0 (IPC)IPC 0SARC0 (ARPEN)ARPEN

Description

Operating mode configuration register

Fields

RE

Receiver Enable
TE

TE
PRELEN

PRELEN
DC

DC
BL

BL
DR

DR
DCRS

DCRS
DO

DO
ECRSFD

ECRSFD
LM

LM
DM

DM
FES

FES
JE

JE
JD

JD
WD

WD
ACS

ACS
CST

CST
S2KP

S2KP
GPSLCE

GPSLCE
IPG

IPG
IPC

IPC
SARC

SARC
ARPEN

ARPEN

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32