MODE=B_0x0, KEYLOCK=B_0x0, REG_EN=B_0x0, CONFIGLOCK=B_0x0
OTFDEC region 3 configuration register
| REG_EN | region on-the-fly decryption enable Note: When this bit is set region context (version, key, nonce) must be valid or garbage will be decrypted. 0 (B_0x0): On-the-fly decryption is disabled for this region. 1 (B_0x1): On-the-fly decryption is enabled for this region. Data are XORed with the corresponding keystream. |
| CONFIGLOCK | region config lock This bit-field is set once, i.e. if this bit is set it can only be reset to “0” if OTFDEC is reset. Setting this bit forces KEYLOCK bit to “1”. 0 (B_0x0): Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are allowed. 1 (B_0x1): Writes to this region CFGR1, STARTADDR, ENDADDR and NONCERx registers are ignored until next OTFDEC reset. |
| KEYLOCK | region key lock This bitfield is set once, i.e. if this bit is set it can only be reset to “0” if the OTFDEC is reset. 0 (B_0x0): Writes to this region KEYRx registers are allowed. 1 (B_0x1): Writes to this region KEYRx registers are ignored until next OTFDEC reset. KEYCRC bitfield is locked. |
| MODE | operating mode This bitfield selects the OTFDEC operating mode for this region: When MODE is not equal to 11 the standard AES encryption mode is activated. When either of the MODE bits are changed the region’s key and associated CRC are zeroed. 0 (B_0x0): Only instruction accesses are decrypted. 1 (B_0x1): Only data accesses are decrypted. 2 (B_0x2): All read accesses are decrypted (instruction or data). 3 (B_0x3): Only instruction accesses are decrypted, and enhanced encryption mode is activated. |
| KEYCRC | region key 8-bit CRC When KEYLOCK=0, KEYCRC bitfield is automatically computed by hardware while loading the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally KEYR3 (all written once). A new computation starts as soon as a new valid sequence is initiated, and KEYCRC is read as zero until a valid sequence is completed. When KEYLOCK=1, KEYCRC remains unchanged until the next reset. CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm X8 + X2 + X + 1 (according the convention). Source code is available in this manual. This field is read only. Note: CRC information is updated only after the last bit of the key has been written. |
| REGx_VERSION | region firmware version This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit is set in the RxCFGR register. |