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stm32 /stm32h7 /STM32H730 /SPI1 /CR1

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Interpret as CR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPE)SPE 0 (MASRX)MASRX 0 (CSTART)CSTART 0 (CSUSP)CSUSP 0 (HDDIR)HDDIR 0 (SSI)SSI 0 (CRC33_17)CRC33_17 0 (RCRCI)RCRCI 0 (TCRCI)TCRCI 0 (IOLOCK)IOLOCK

Description

control register 1

Fields

SPE

Serial Peripheral Enable
MASRX

Master automatic SUSP in Receive mode
CSTART

Master transfer start
CSUSP

Master SUSPend request
HDDIR

Rx/Tx direction at Half-duplex mode
SSI

Internal SS signal input level
CRC33_17

32-bit CRC polynomial configuration
RCRCI

CRC calculation initialization pattern control for receiver
TCRCI

CRC calculation initialization pattern control for transmitter
IOLOCK

Locking the AF configuration of associated IOs

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32