stm32 /stm32h7 /STM32H733 /Flash /SR

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Interpret as SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BSY)BSY 0 (WBNE)WBNE 0 (QW)QW 0 (CRC_BUSY)CRC_BUSY 0 (EOP)EOP 0 (WRPERR)WRPERR 0 (PGSERR)PGSERR 0 (STRBERR)STRBERR 0 (INCERR)INCERR 0 (OPERR)OPERR 0 (RDPERR)RDPERR 0 (RDSERR)RDSERR 0 (SNECCERR)SNECCERR 0 (DBECCERR)DBECCERR 0 (CRCEND)CRCEND 0 (CRCRDERR)CRCRDERR

Description

FLASH status register for bank 1

Fields

BSY

ongoing program flag

WBNE

write buffer not empty flag

QW

wait queue flag

CRC_BUSY

CRC busy flag

EOP

end-of-program flag

WRPERR

write protection error flag

PGSERR

programming sequence error flag

STRBERR

strobe error flag

INCERR

inconsistency error flag

OPERR

write/erase error flag

RDPERR

read protection error flag

RDSERR

secure error flag

SNECCERR

single correction error flag

DBECCERR

ECC double detection error flag

CRCEND

CRC-complete flag

CRCRDERR

CRC read error flag CRCRDERR1 flag is raised when a word is found read protected during a CRC operation on bank 1. An interrupt is generated if CRCRDIE1 and CRCEND1 are set to 1. Writing 1 to CLR_CRCRDERR1 bit in FLASH_CCR1 register clears CRCRDERR1. Note: This flag is valid only when CRCEND1 bit is set to 1

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