stm32 /stm32h7 /STM32H733 /OTFDEC1 /OTFDEC_ICR

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Interpret as OTFDEC_ICR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SEIF 0 (B_0x0)XONEIF 0 (B_0x0)KEIF

KEIF=B_0x0, SEIF=B_0x0, XONEIF=B_0x0

Description

OTFDEC interrupt clear register

Fields

SEIF

Security Error Interrupt Flag clear This bit is written by application, and always reads as 0.

0 (B_0x0): SEIF flag status is not affected

1 (B_0x1): SEIF flag status is cleared in OTFDEC_ISR register

XONEIF

Execute-only execute-Never Error Interrupt Flag clear This bit is written by application, and always reads as 0.

0 (B_0x0): XONEIF flag status is not affected

1 (B_0x1): XONEIF flag status is cleared in OTFDEC_ISR register

KEIF

Key Error Interrupt Flag clear This bit is written by application, and always reads as 0. Note: Clearing KEIF does not solve the source of the problem (bad key registers). To be able to read or execute again any encrypted region, OTFDEC key registers must properly initialized, again.

0 (B_0x0): KEIF flag status is not affected

1 (B_0x1): KEIF flag status is cleared in OTFDEC_ISR register

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