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stm32 /stm32h7 /STM32H733 /RCC /APB2RSTR

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Interpret as APB2RSTR

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https://regviz.com/r/stm32/stm32h7/STM32H723/RCC/APB2RSTR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1RST)TIM1RST 0 (TIM8RST)TIM8RST 0 (USART1RST)USART1RST 0 (USART6RST)USART6RST 0 (UART9RST)UART9RST 0 (USART10RST)USART10RST 0 (SPI1RST)SPI1RST 0 (SPI4RST)SPI4RST 0 (TIM15RST)TIM15RST 0 (TIM16RST)TIM16RST 0 (TIM17RST)TIM17RST 0 (SPI5RST)SPI5RST 0 (SAI1RST)SAI1RST 0 (DFSDM1RST)DFSDM1RST

Description

RCC APB2 Peripheral Reset Register

Fields

TIM1RST

TIM1 block reset
TIM8RST

TIM8 block reset
USART1RST

USART1 block reset
USART6RST

USART6 block reset
UART9RST

UART9 block reset Set and reset by software.
USART10RST

USART10 block reset Set and reset by software.
SPI1RST

SPI1 block reset
SPI4RST

SPI4 block reset
TIM15RST

TIM15 block reset
TIM16RST

TIM16 block reset
TIM17RST

TIM17 block reset
SPI5RST

SPI5 block reset
SAI1RST

SAI1 block reset
DFSDM1RST

DFSDM1 block reset Set and reset by software.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32