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stm32 /stm32h7 /STM32H733 /RCC /C1_APB3LPENR

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Interpret as C1_APB3LPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LTDCLPEN)LTDCLPEN 0 (WWDG1LPEN)WWDG1LPEN

Description

RCC APB3 Sleep Clock Register

Fields

LTDCLPEN

LTDC peripheral clock enable during CSleep mode
WWDG1LPEN

WWDG1 Clock Enable During CSleep Mode

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32