SMP13=B_0x0, SMP15=B_0x0, SMP12=B_0x0, SMP10=B_0x0, SMP16=B_0x0, SMP18=B_0x0, SMP11=B_0x0, SMP17=B_0x0, SMP14=B_0x0
ADC sample time register 2
| SMP10 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP11 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP12 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP13 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP14 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP15 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP16 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP17 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |
| SMP18 | Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value. 0 (B_0x0): 2.5 ADC clock cycles 1 (B_0x1): 6.5 ADC clock cycles 2 (B_0x2): 12.5 ADC clock cycles 3 (B_0x3): 24.5 ADC clock cycles 4 (B_0x4): 47.5 ADC clock cycles 5 (B_0x5): 92.5 ADC clock cycles 6 (B_0x6): 247.5 ADC clock cycles 7 (B_0x7): 640.5 ADC clock cycles |