stm32 /stm32h7 /STM32H735 /RCC /APB2ENR

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Interpret as APB2ENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIM1EN)TIM1EN 0 (TIM8EN)TIM8EN 0 (USART1EN)USART1EN 0 (USART6EN)USART6EN 0 (UART9EN)UART9EN 0 (USART10EN)USART10EN 0 (SPI1EN)SPI1EN 0 (SPI4EN)SPI4EN 0 (TIM15EN)TIM15EN 0 (TIM16EN)TIM16EN 0 (TIM17EN)TIM17EN 0 (SPI5EN)SPI5EN 0 (SAI1EN)SAI1EN 0 (DFSDM1EN)DFSDM1EN

Description

RCC APB2 Clock Register

Fields

TIM1EN

TIM1 peripheral clock enable

TIM8EN

TIM8 peripheral clock enable

USART1EN

USART1 Peripheral Clocks Enable

USART6EN

USART6 Peripheral Clocks Enable

UART9EN

UART9 peripheral clocks enable Set and reset by software. The peripheral clocks of the UART9 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.

USART10EN

USART10 peripheral clocks enable Set and reset by software. The peripheral clocks of the USART10 are the kernel clock selected by USART16910SEL and provided to UCKL input, and the rcc_pclk2 bus interface clock.

SPI1EN

SPI1 Peripheral Clocks Enable

SPI4EN

SPI4 Peripheral Clocks Enable

TIM15EN

TIM15 peripheral clock enable Set and reset by software.

TIM16EN

TIM16 peripheral clock enable

TIM17EN

TIM17 peripheral clock enable

SPI5EN

SPI5 Peripheral Clocks Enable

SAI1EN

SAI1 Peripheral Clocks Enable

DFSDM1EN

DFSDM1 peripheral clocks enable Set and reset by software. DFSDM1 peripheral clocks are the kernel clocks selected by SAI1SEL and DFSDM1SEL and provided to Aclk and clk inputs respectively,

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