FLASH control register
| LOCK | configuration lock bit |
| PG | program enable bit |
| SER | sector erase request |
| BER | erase request |
| PSIZE | program size |
| FW | write forcing control bit |
| START | bank or sector erase start control bit |
| SNB | sector erase selection number |
| CRC_EN | CRC control bit |
| EOPIE | end-of-program interrupt control bit |
| WRPERRIE | write protection error interrupt enable bit |
| PGSERRIE | programming sequence error interrupt enable bit |
| STRBERRIE | strobe error interrupt enable bit |
| INCERRIE | inconsistency error interrupt enable bit |
| OPERRIE | write/erase error interrupt enable bit |
| RDPERRIE | read protection error interrupt enable bit |
| RDSERRIE | secure error interrupt enable bit |
| SNECCERRIE | ECC single correction error interrupt enable bit |
| DBECCERRIE | ECC double detection error interrupt enable bit |
| CRCENDIE | end of CRC calculation interrupt enable bit |
| CRCRDERRIE | CRC read error interrupt enable bit When CRCRDERRIE1 bit is set to 1, an interrupt is generated when a protected area (PCROP or secure-only) has been detected during the last CRC computation on bank 1. CRCRDERRIE1 can be programmed only when LOCK1 is cleared to 0. |