TCIE=B_0x0, EN=B_0x0, PSIZE=B_0x0, MINC=B_0x0, CIRC=B_0x0, MEM2MEM=B_0x0, CT=B_0x0, DIR=B_0x0, MSIZE=B_0x0, TEIE=B_0x0, HTIE=B_0x0, DBM=B_0x0, PL=B_0x0, PINC=B_0x0
BDMA channel 2 configuration register
| EN | channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the BDMA_ISR register is cleared (by setting the CTEIFx bit of the BDMA_IFCR register). Note: this bit is set and cleared by software. 0 (B_0x0): disabled 1 (B_0x1): enabled |
| TCIE | transfer complete interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| HTIE | half transfer interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| TEIE | transfer error interrupt enable Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| DIR | data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the BDMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the BDMA_CM0/1ARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the BDMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the BDMA_CM0/1ARx register. This is still valid in a peripheral-to-peripheral mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): read from peripheral 1 (B_0x1): read from memory |
| CIRC | circular mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| PINC | peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| MINC | memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| PSIZE | peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits 2 (B_0x2): 32 bits |
| MSIZE | memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits 2 (B_0x2): 32 bits |
| PL | priority level Note: this field is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): low 1 (B_0x1): medium 2 (B_0x2): high 3 (B_0x3): very high |
| MEM2MEM | memory-to-memory mode Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled 1 (B_0x1): enabled |
| DBM | double-buffer mode This bit must be set only in memory-to-peripheral and peripheral-to-memory transfers (MEM2MEM=0). The CIRC bit must also be set in double buffer mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1). 0 (B_0x0): disabled (no memory address switch at the end of the BDMA transfer) 1 (B_0x1): enabled (memory address switched at the end of the BDMA transfer) |
| CT | current target memory of DMA transfer in double-buffer mode This bit is toggled by hardware at the end of each channel transfer in double-buffer mode. Note: this bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1). 0 (B_0x0): memory 0 (addressed by the BDMA_CM0AR pointer) 1 (B_0x1): memory 1 (addressed by the BDMA_CM1AR pointer) |