stm32 /stm32h7 /STM32H743 /Flash /SR1

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Interpret as SR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BSY1)BSY1 0 (WBNE1)WBNE1 0 (QW1)QW1 0 (CRC_BUSY1)CRC_BUSY1 0 (EOP1)EOP1 0 (WRPERR1)WRPERR1 0 (PGSERR1)PGSERR1 0 (STRBERR1)STRBERR1 0 (INCERR1)INCERR1 0 (OPERR1)OPERR1 0 (RDPERR1)RDPERR1 0 (RDSERR1)RDSERR1 0 (SNECCERR)SNECCERR 0 (DBECCERR1)DBECCERR1 0 (CRCEND1)CRCEND1 0 (CRCRDERR1)CRCRDERR1

Description

FLASH status register for bank 1

Fields

BSY1

Bank 1 ongoing program flag

WBNE1

Bank 1 write buffer not empty flag

QW1

Bank 1 wait queue flag

CRC_BUSY1

Bank 1 CRC busy flag

EOP1

Bank 1 end-of-program flag

WRPERR1

Bank 1 write protection error flag

PGSERR1

Bank 1 programming sequence error flag

STRBERR1

Bank 1 strobe error flag

INCERR1

Bank 1 inconsistency error flag

OPERR1

Bank 1 write/erase error flag

RDPERR1

Bank 1 read protection error flag

RDSERR1

Bank 1 secure error flag

SNECCERR

Bank 1 single correction error flag

DBECCERR1

Bank 1 ECC double detection error flag

CRCEND1

Bank 1 CRC-complete flag

CRCRDERR1

Bank 1 CRC read error flag CRCRDERR1 flag is raised when a word is found read protected during a CRC operation on bank 1. An interrupt is generated if CRCRDIE1 and CRCEND1 are set to 1. Writing 1 to CLR_CRCRDERR1 bit in FLASH_CCR1 register clears CRCRDERR1. Note: This flag is valid only when CRCEND1 bit is set to 1

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