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stm32 /stm32h7 /STM32H745_CM7 /DSIHOST /DSI_WISR

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Interpret as DSI_WISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEIF)TEIF 0 (ERIF)ERIF 0 (BUSY)BUSY 0 (PLLLS)PLLLS 0 (PLLLIF)PLLLIF 0 (PLLUIF)PLLUIF 0 (RRS)RRS 0 (RRIF)RRIF

Description

DSI wrapper interrupt and status register

Fields

TEIF

TEIF
ERIF

ERIF
BUSY

BUSY
PLLLS

PLLLS
PLLLIF

PLLLIF
PLLUIF

PLLUIF
RRS

RRS
RRIF

RRIF

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32