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stm32 /stm32h7 /STM32H747_CM4 /FDCAN1 /FDCAN_TTOCN

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Interpret as FDCAN_TTOCN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SGT)SGT 0 (ECS)ECS 0 (SWP)SWP 0SWS0 (RTIE)RTIE 0TMC0 (TTIE)TTIE 0 (GCS)GCS 0 (FGP)FGP 0 (TMG)TMG 0 (NIG)NIG 0 (ESCN)ESCN 0 (LCKC)LCKC

Description

FDCAN TT Operation Control Register

Fields

SGT

Set Global time
ECS

External Clock Synchronization
SWP

Stop Watch Polarity
SWS

Stop Watch Source.
RTIE

Register Time Mark Interrupt Pulse Enable
TMC

Register Time Mark Compare
TTIE

Trigger Time Mark Interrupt Pulse Enable
GCS

Gap Control Select
FGP

Finish Gap.
TMG

Time Mark Gap
NIG

Next is Gap
ESCN

External Synchronization Control
LCKC

TT Operation Control Register Locked

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32