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stm32 /stm32h7 /STM32H747_CM4 /HRTIM_Common /BMCR

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Interpret as BMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BME)BME 0 (BMOM)BMOM 0BMCLK0BMPRSC0 (BMPREN)BMPREN 0 (MTBM)MTBM 0 (TABM)TABM 0 (TBBM)TBBM 0 (TCBM)TCBM 0 (TDBM)TDBM 0 (TEBM)TEBM 0 (BMSTAT)BMSTAT

Description

Burst Mode Control Register

Fields

BME

Burst Mode enable
BMOM

Burst Mode operating mode
BMCLK

Burst Mode Clock source
BMPRSC

Burst Mode Prescaler
BMPREN

Burst Mode Preload Enable
MTBM

Master Timer Burst Mode
TABM

Timer A Burst Mode
TBBM

Timer B Burst Mode
TCBM

Timer C Burst Mode
TDBM

Timer D Burst Mode
TEBM

Timer E Burst Mode
BMSTAT

Burst Mode Status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32