Regviz

stm32 /stm32h7 /STM32H747_CM7 /FMC /SDSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SDSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h7/STM32H723/FMC/SDSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RE)RE 0MODES1 0MODES2

Description

SDRAM Status register

Fields

RE

Refresh error flag An interrupt is generated if REIE = 1 and RE = 1
MODES1

Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1.
MODES2

Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32