Regviz

stm32 /stm32h7 /STM32H747_CM7 /RCC /D3AMR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as D3AMR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h7/STM32H745_CM4/RCC/D3AMR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BDMAAMEN)BDMAAMEN 0 (LPUART1AMEN)LPUART1AMEN 0 (SPI6AMEN)SPI6AMEN 0 (I2C4AMEN)I2C4AMEN 0 (LPTIM2AMEN)LPTIM2AMEN 0 (LPTIM3AMEN)LPTIM3AMEN 0 (LPTIM4AMEN)LPTIM4AMEN 0 (LPTIM5AMEN)LPTIM5AMEN 0 (COMP12AMEN)COMP12AMEN 0 (VREFAMEN)VREFAMEN 0 (RTCAMEN)RTCAMEN 0 (CRCAMEN)CRCAMEN 0 (SAI4AMEN)SAI4AMEN 0 (ADC3AMEN)ADC3AMEN 0 (BKPSRAMAMEN)BKPSRAMAMEN 0 (SRAM4AMEN)SRAM4AMEN

Description

RCC D3 Autonomous mode Register

Fields

BDMAAMEN

BDMA and DMAMUX Autonomous mode enable
LPUART1AMEN

LPUART1 Autonomous mode enable
SPI6AMEN

SPI6 Autonomous mode enable
I2C4AMEN

I2C4 Autonomous mode enable
LPTIM2AMEN

LPTIM2 Autonomous mode enable
LPTIM3AMEN

LPTIM3 Autonomous mode enable
LPTIM4AMEN

LPTIM4 Autonomous mode enable
LPTIM5AMEN

LPTIM5 Autonomous mode enable
COMP12AMEN

COMP12 Autonomous mode enable
VREFAMEN

VREF Autonomous mode enable
RTCAMEN

RTC Autonomous mode enable
CRCAMEN

CRC Autonomous mode enable
SAI4AMEN

SAI4 Autonomous mode enable
ADC3AMEN

ADC3 Autonomous mode enable
BKPSRAMAMEN

Backup RAM Autonomous mode enable
SRAM4AMEN

SRAM4 Autonomous mode enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32