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stm32 /stm32h7 /STM32H753 /Ethernet_DMA /DMADSR

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Interpret as DMADSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AXWHSTS)AXWHSTS 0RPS00TPS0

Description

Debug status register

Fields

AXWHSTS

AHB Master Write Channel
RPS0

DMA Channel Receive Process State
TPS0

DMA Channel Transmit Process State

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32