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stm32 /stm32h7 /STM32H755_CM4 /DBGMCU /APB2FZ2

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Interpret as APB2FZ2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM1)DBG_TIM1 0 (DBG_TIM8)DBG_TIM8 0 (DBG_TIM15)DBG_TIM15 0 (DBG_TIM16)DBG_TIM16 0 (DBG_TIM17)DBG_TIM17 0 (DBG_HRTIM)DBG_HRTIM

Description

DBGMCU APB2 peripheral freeze register CPU2

Fields

DBG_TIM1

TIM1 stop in debug
DBG_TIM8

TIM8 stop in debug
DBG_TIM15

TIM15 stop in debug
DBG_TIM16

TIM16 stop in debug
DBG_TIM17

TIM17 stop in debug
DBG_HRTIM

HRTIM stop in debug

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32