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stm32 /stm32h7 /STM32H755_CM4 /DBGMCU /APB3FZ2

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Interpret as APB3FZ2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WWDG1)WWDG1

Description

DBGMCU APB3 peripheral freeze register CPU2

Fields

WWDG1

WWDG1 stop in debug

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32