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stm32 /stm32h7 /STM32H755_CM4 /DSIHOST /DSI_DLTCR

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Interpret as DSI_DLTCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MRD_TIME0LP2HS_TIME0HS2LP_TIME

Description

DSI Host data lane timer configuration register

Fields

MRD_TIME

Maximum read time
LP2HS_TIME

LP2HS_TIME
HS2LP_TIME

HS2LP_TIME

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32