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stm32 /stm32h7 /STM32H755_CM4 /DSIHOST /DSI_WPCR1

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Interpret as DSI_WPCR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0HSTXDCL 0HSTXDDL 0LPSRCCL 0LPSRCDL 0 (SDDC)SDDC 0HSTXSRCCL 0HSTXSRCDL 0 (FLPRXLPM)FLPRXLPM 0LPRXFT

Description

This register shall be programmed only when DSI is stopped (CR. DSIEN=0 and CR.EN = 0).

Fields

HSTXDCL

High-speed transmission delay on clock lane
HSTXDDL

High-speed transmission delay on data lanes
LPSRCCL

Low-power transmission slew-rate compensation on clock lane
LPSRCDL

Low-power transmission slew-rate compensation on data lanes
SDDC

SDD control
HSTXSRCCL

High-speed transmission slew-rate control on clock lane
HSTXSRCDL

High-speed transmission slew-rate control on data lanes
FLPRXLPM

Forces LP receiver in low-power mode
LPRXFT

Low-power RX low-pass filtering tuning

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32