EXTI event mask register
| MR0 | CPU Event mask on Event input x |
| MR1 | CPU Event mask on Event input x |
| MR2 | CPU Event mask on Event input x |
| MR3 | CPU Event mask on Event input x |
| MR4 | CPU Event mask on Event input x |
| MR5 | CPU Event mask on Event input x |
| MR6 | CPU Event mask on Event input x |
| MR7 | CPU Event mask on Event input x |
| MR8 | CPU Event mask on Event input x |
| MR9 | CPU Event mask on Event input x |
| MR10 | CPU Event mask on Event input x |
| MR11 | CPU Event mask on Event input x |
| MR12 | CPU Event mask on Event input x |
| MR13 | CPU Event mask on Event input x |
| MR14 | CPU Event mask on Event input x |
| MR15 | CPU Event mask on Event input x |
| MR16 | CPU Event mask on Event input x |
| MR17 | CPU Event mask on Event input x |
| MR18 | CPU Event mask on Event input x |
| MR19 | CPU Event mask on Event input x |
| MR20 | CPU Event mask on Event input x |
| MR21 | CPU Event mask on Event input x |
| MR22 | CPU Event mask on Event input x |
| MR23 | CPU Event mask on Event input x |
| MR24 | CPU Event mask on Event input x |
| MR25 | CPU Event mask on Event input x |
| MR26 | CPU Event mask on Event input x |
| MR27 | CPU Event mask on Event input x |
| MR28 | CPU Event mask on Event input x |
| MR29 | CPU Event mask on Event input x |
| MR30 | CPU Event mask on Event input x |
| MR31 | CPU Event mask on Event input x |