EXTI D3 pending mask register
| MR0 | Rising trigger event configuration bit of Configurable Event input |
| MR1 | Rising trigger event configuration bit of Configurable Event input |
| MR2 | Rising trigger event configuration bit of Configurable Event input |
| MR3 | Rising trigger event configuration bit of Configurable Event input |
| MR4 | Rising trigger event configuration bit of Configurable Event input |
| MR5 | Rising trigger event configuration bit of Configurable Event input |
| MR6 | Rising trigger event configuration bit of Configurable Event input |
| MR7 | Rising trigger event configuration bit of Configurable Event input |
| MR8 | Rising trigger event configuration bit of Configurable Event input |
| MR9 | Rising trigger event configuration bit of Configurable Event input |
| MR10 | Rising trigger event configuration bit of Configurable Event input |
| MR11 | Rising trigger event configuration bit of Configurable Event input |
| MR12 | Rising trigger event configuration bit of Configurable Event input |
| MR13 | Rising trigger event configuration bit of Configurable Event input |
| MR14 | Rising trigger event configuration bit of Configurable Event input |
| MR15 | Rising trigger event configuration bit of Configurable Event input |
| MR19 | Rising trigger event configuration bit of Configurable Event input |
| MR20 | Rising trigger event configuration bit of Configurable Event input |
| MR21 | Rising trigger event configuration bit of Configurable Event input |
| MR25 | Rising trigger event configuration bit of Configurable Event input |