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stm32 /stm32h7 /STM32H755_CM4 /HRTIM_Common /BDTxUPR

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Interpret as BDTxUPR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TIMxCR)TIMxCR 0 (TIMxICR)TIMxICR 0 (TIMxDIER)TIMxDIER 0 (TIMxCNT)TIMxCNT 0 (TIMxPER)TIMxPER 0 (TIMxREP)TIMxREP 0 (TIMxCMP1)TIMxCMP1 0 (TIMxCMP2)TIMxCMP2 0 (TIMxCMP3)TIMxCMP3 0 (TIMxCMP4)TIMxCMP4 0 (TIMx_DTxR)TIMx_DTxR 0 (TIMxSET1R)TIMxSET1R 0 (TIMxRST1R)TIMxRST1R 0 (TIMxSET2R)TIMxSET2R 0 (TIMxRST2R)TIMxRST2R 0 (TIMxEEFR1)TIMxEEFR1 0 (TIMxEEFR2)TIMxEEFR2 0 (TIMxRSTR)TIMxRSTR 0 (TIMxCHPR)TIMxCHPR 0 (TIMxOUTR)TIMxOUTR 0 (TIMxFLTR)TIMxFLTR

Description

Burst DMA Timerx update Register

Fields

TIMxCR

HRTIM_TIMxCR register update enable
TIMxICR

HRTIM_TIMxICR register update enable
TIMxDIER

HRTIM_TIMxDIER register update enable
TIMxCNT

HRTIM_CNTxR register update enable
TIMxPER

HRTIM_PERxR register update enable
TIMxREP

HRTIM_REPxR register update enable
TIMxCMP1

HRTIM_CMP1xR register update enable
TIMxCMP2

HRTIM_CMP2xR register update enable
TIMxCMP3

HRTIM_CMP3xR register update enable
TIMxCMP4

HRTIM_CMP4xR register update enable
TIMx_DTxR

HRTIM_DTxR register update enable
TIMxSET1R

HRTIM_SET1xR register update enable
TIMxRST1R

HRTIM_RST1xR register update enable
TIMxSET2R

HRTIM_SET2xR register update enable
TIMxRST2R

HRTIM_RST2xR register update enable
TIMxEEFR1

HRTIM_EEFxR1 register update enable
TIMxEEFR2

HRTIM_EEFxR2 register update enable
TIMxRSTR

HRTIM_RSTxR register update enable
TIMxCHPR

HRTIM_CHPxR register update enable
TIMxOUTR

HRTIM_OUTxR register update enable
TIMxFLTR

HRTIM_FLTxR register update enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32