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stm32 /stm32h7 /STM32H755_CM4 /RCC /AHB3RSTR

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Interpret as AHB3RSTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MDMARST)MDMARST 0 (DMA2DRST)DMA2DRST 0 (JPGDECRST)JPGDECRST 0 (FMCRST)FMCRST 0 (QSPIRST)QSPIRST 0 (SDMMC1RST)SDMMC1RST 0 (CPURST)CPURST

Description

RCC AHB3 Reset Register

Fields

MDMARST

MDMA block reset
DMA2DRST

DMA2D block reset
JPGDECRST

JPGDEC block reset
FMCRST

FMC block reset
QSPIRST

QUADSPI and QUADSPI delay block reset
SDMMC1RST

SDMMC1 and SDMMC1 delay block reset
CPURST

CPU reset

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32