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stm32 /stm32h7 /STM32H755_CM7 /BDMA /IFCR

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Interpret as IFCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CGIF1)CGIF1 0 (CTCIF1)CTCIF1 0 (CHTIF1)CHTIF1 0 (CTEIF1)CTEIF1 0 (CGIF2)CGIF2 0 (CTCIF2)CTCIF2 0 (CHTIF2)CHTIF2 0 (CTEIF2)CTEIF2 0 (CGIF3)CGIF3 0 (CTCIF3)CTCIF3 0 (CHTIF3)CHTIF3 0 (CTEIF3)CTEIF3 0 (CGIF4)CGIF4 0 (CTCIF4)CTCIF4 0 (CHTIF4)CHTIF4 0 (CTEIF4)CTEIF4 0 (CGIF5)CGIF5 0 (CTCIF5)CTCIF5 0 (CHTIF5)CHTIF5 0 (CTEIF5)CTEIF5 0 (CGIF6)CGIF6 0 (CTCIF6)CTCIF6 0 (CHTIF6)CHTIF6 0 (CTEIF6)CTEIF6 0 (CGIF7)CGIF7 0 (CTCIF7)CTCIF7 0 (CHTIF7)CHTIF7 0 (CTEIF7)CTEIF7 0 (CGIF8)CGIF8 0 (CTCIF8)CTCIF8 0 (CHTIF8)CHTIF8 0 (CTEIF8)CTEIF8

Description

DMA interrupt flag clear register

Fields

CGIF1

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF1

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF1

Channel x half transfer clear This bit is set and cleared by software.
CTEIF1

Channel x transfer error clear This bit is set and cleared by software.
CGIF2

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF2

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF2

Channel x half transfer clear This bit is set and cleared by software.
CTEIF2

Channel x transfer error clear This bit is set and cleared by software.
CGIF3

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF3

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF3

Channel x half transfer clear This bit is set and cleared by software.
CTEIF3

Channel x transfer error clear This bit is set and cleared by software.
CGIF4

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF4

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF4

Channel x half transfer clear This bit is set and cleared by software.
CTEIF4

Channel x transfer error clear This bit is set and cleared by software.
CGIF5

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF5

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF5

Channel x half transfer clear This bit is set and cleared by software.
CTEIF5

Channel x transfer error clear This bit is set and cleared by software.
CGIF6

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF6

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF6

Channel x half transfer clear This bit is set and cleared by software.
CTEIF6

Channel x transfer error clear This bit is set and cleared by software.
CGIF7

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF7

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF7

Channel x half transfer clear This bit is set and cleared by software.
CTEIF7

Channel x transfer error clear This bit is set and cleared by software.
CGIF8

Channel x global interrupt clear This bit is set and cleared by software.
CTCIF8

Channel x transfer complete clear This bit is set and cleared by software.
CHTIF8

Channel x half transfer clear This bit is set and cleared by software.
CTEIF8

Channel x transfer error clear This bit is set and cleared by software.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32