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stm32 /stm32h7 /STM32H755_CM7 /DSIHOST /DSI_CLCR

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Interpret as DSI_CLCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DPCC)DPCC 0 (ACR)ACR

Description

DSI Host clock lane configuration register

Fields

DPCC

DPCC
ACR

ACR

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32